1. Field of the Invention
The present invention relates to a process of fabricating a semiconductor unit employing a flip-chip function.
Recently, high-speed operation has been demanded of semiconductor units so that not only high-speed operation of semiconductor devices themselves but also shortening of circuit lengths between the semiconductor devices are required. For this purpose, miniaturization of semiconductor devices and narrowing of bonding pitches are needed. The shortening of the total circuit length may be achieved by soldering electronic devices to substrates using lead-less chip carriers (LCC) and flip chip bonding.
2. Related Art
In order to join an electronic device such as a semiconductor device onto a substrate, solder bumps are formed on at least a first one of the electronic device and the substrate. Then, the first one is positioned on the second one of the electronic device and the substrate so that the thus formed bumps may meet the corresponding electrodes provided on the second one. Then, the bumps are made to reflow so that the bumps join the electronic device onto the substrate. There, flux is used.
The flux acts to provisionally maintain the spatial relationship between the electronic device and the substrate by lying between the bumps and the second one of the electronic device and the substrate. The flux further acts to create sufficient wetting conditions between the solder bumps and the corresponding electrodes. The flux may cause problems as described below. The flux is cleaned away (i.e., removed) after the relevant bonding has been completed. If any residue of the flux is left after the cleaning, the active ingredients contained in the residue may cause corrosion there. Further, the toxicity of the flux may pollute the environment if the liquid waste produced in the above cleaning is discharged.
Further, the flux cleaning work for the relevant solder bonding may become difficult if the distances between the components or semiconductor devices and the substrates are made narrow so as to shorten the total circuit length. In particular, if the flip chip bonding is applied to the solder bonding, since the distance between the semiconductor device and the substrate to be joined together is thus short, the flux cleaning work is difficult and checking the effectiveness of the flux cleaning is also difficult.
On the other hand, omission of the flux application in the solder bonding process may result in poor bonding because of insufficient wetting conditions between the bumps and electrodes. Further, displacement positioning errors may occur between the electronic device and substrate during the period between the initial positioning process and the actual solder bonding process.
In order to achieve sufficient wetting conditions between the electronic device and substrate without using flux at the solder joining process, the following methods may be used, for example: before the solder joining process, oxide and hydroxide are removed from the bumps using flux, dry-etching, or the like, and then the solder joining is performed in an inert atmosphere. (See Japanese Laid-Open Patent Application No. 62-71908, Japanese Laid-Open Patent Application No. 62-276518, Japanese Laid-Open Patent Application No. 2-303676, Japanese Laid-Open Patent Application No. 3-138941, Japanese Laid-Open Patent Application No. 3-138942, and Japanese Laid-Open Patent Application No. 3-171643)
However, since no means, such as flux, is used to provisionally fix the electronic device onto the substrate, the above mentioned positioning errors may occur. Further, large-scale equipment is needed for removing oxide films formed on the solder bump surfaces by means of the dry-etching method.
In order to avoid the positioning errors without using the flux, a thermo-compression fixing method and a fixing method employing a soft metal or the like may be used. (See Japanese Laid-Open Patent Application No. 59-072795, Japanese Laid-Open Patent Application No. 62-245640, Japanese Laid-Open Patent Application No. 1-192126, Japanese Laid-Open Patent Application No. 2-232946, Japanese Laid-Open Patent Application No. 3-71649, Japanese Laid-Open Patent Application No. 3-171643, and Japanese Laid-Open Patent Application No. 3-217024.)
The provisional fixing of the electronic device and substrate may include problems such as are described below. If the respective heights of the solder bumps formed on the first one of the electronic device and substrate are different from one another, some bumps may not come into contact with the corresponding electrodes after the provisional fixing process has been performed. Also, if the respective heights of the bumps measured before the bonding process are less than the distance between the electronic device and substrate measured after the solder bonding process, there may have been a problem in the solder bonding process. In that case, the inspection work to find the problems appearing in both the provisional fixing process and the solder joining process is difficult. Thus, the reliability of the resulting semiconductor unit may be degraded.